Field of the Invention
The invention relates to a method for fabricating a nonvolatile memory cell with a separate tunnel window and particularly a method for fabricating an EEPROM (Electrically Erasable Programmable Read-Only Memory) cell with a small space requirement and a high number of program/clear cycles.
Rewritable non-volatile semiconductor memory cells are gaining increasing significance in highly integrated circuits because of their ability to store modifiable data in chip cards over a long time period without requiring a voltage supply.
It is possible to distinguish between EEPROMs, EPROMs and FLASH-EPROM memories, depending on the non-volatile semiconductor memory cells that are used.
FIG. 5 is a sectional view of a conventional EEPROM memory cell SZ, which is substantially formed of a tunnel window cell TF and a transistor memory cell TZ. According to FIG. 5, the transistor memory cell TZ is formed of a relatively thick gate layer 3, which is relatively insensitive to leakage currents, an overlying floating gate layer 5, a dielectric layer 6, and a control electrode layer 7. A charge which is introduced into the floating gate layer 5 determines the switching behavior of the corresponding field effect transistor, which is driven by way of source/drain zones 1 and the control electrode layer 7. For introducing the charges in the floating gate layer 5, the memory cell includes the tunnel window cell TF, which has substantially the same layer sequence as the transistor memory cell TZ, though there is an insulating layer formed of a very thin tunnel layer 4 between a semiconductor substrate 100 and the floating gate layer 5.
In the fabrication of this conventional EEPROM memory cell SZ, first an ion implantation is carried out in the region of the tunnel window cell TF for purposes of forming a homogenous tunnel zone 2xe2x80x2. Next, the insulating tunnel layer 4, i.e. gate layer 3, and the floating gate layer 5, dielectric layer 6, and control electrode layer 7 are applied. Lastly, in one (or more) additional ion implantations the source/drain zones 1 are formed in the semiconductor substrate 100 in self-aligning fashion with the aid of the memory cell SZ as the mask. This way, an extremely high-grade rewritable non-volatile semiconductor memory cell is obtained, which has a very good endurance. The endurance refers to the number of program/clear cycles and is approx. 106 cycles in conventional EEPROMs of this kind.
The disadvantage of these conventional EPROMs is the large area required for the memory cell SZ, for which reason they can be utilized in highly integrated circuits only under certain conditions.
In contrast, FLASH-EPROM memory cells have an extraordinarily small area requirement. FIG. 6 represents a section of a conventional FLASH-EPROM memory cell, wherein a tunnel oxide layer 4, a floating gate layer 5, a dielectric layer 6 and a control electrode layer 7 are stacked on a semiconductor substrate 100. In order to form a tunnel zone in a tunnel window region TF"" of the FLASH-EPROM memory cell, implantation zones 2 are formed in the semiconductor substrate 100 in self-aligning fashion with the aid of the stacked memory cell. Next, source/drain zones 1 are incorporated in the semiconductor substrate 100 in self-aligning fashion with the aid of the memory cell and additional auxiliary layers or spacers 8. In this conventional FLASH-EPROM memory cell, as in the above described EEPROM memory cell, a charge is implanted in the floating gate layer 5 by the injection of hot charge carriers and/or Fowler-Nordheim tunneling in the tunnel window region TF"" via the tunnel layer 4. The implanted charge carriers will subsequently determine the switching behavior of a transistor cell region TZ"".
Despite the significantly smaller area required by this conventional FLASH-EPROM memory cell, this type of non-volatile memory cell has a substantial disadvantage in that its endurance (i.e. the number of program/clear cycles) is significantly poorer than that of the conventional EEPROM memory cell represented in FIG. 4. Usually the endurance of these FLASH-EPROM memory cells is approx. 103 cycles.
A significant disadvantage of these rewritable conventional non-volatile memory cells is that they can be combined into a common integrated circuit only under certain conditions. This is particularly attributable to the fact that the implantation of the tunnel zone 2xe2x80x2, which is carried out beforehand according to FIG. 5, influences the thickness of the subsequent tunnel layer 4. In other words, given the utilization of the same fabrication process, a tunnel layer 4 for a tunnel window cell TF as represented in FIG. 5 will have a different thickness than in the FLASH-EPROM memory cell represented in FIG. 6. Furthermore, the implantation zone 2xe2x80x2 represented in FIG. 5 is very sensitive to thermal post-processing, whereas the implantation zone 2 represented in FIG. 6 is formed relatively late in the fabrication process. For these reasons, different program/clear voltages arise for the memory cells according to FIG. 4 and FIG. 5, which are formed in the same integrated circuit.
U.S. Pat. No. 5,565,371 also describes a method for fabricating a non-volatile semiconductor memory cell with a separate tunnel window, wherein the transistor memory cell is programmed by the injection of hot charge carriers, and the transistor memory cell is cleared via Fowler-Nordheim tunneling. The disadvantage of this is the extraordinarily large area requirement and the introduction of a number of nonstandard fabrication processes. It is therefore impossible to combine this method with conventional methods.
It is accordingly an object of the invention to provide a method for fabricating a non-volatile semiconductor memory cell having a separate tunnel window which overcomes the above-mentioned disadvantages of the heretofore-known memory cells of this general type and which reduces the area requirement of the memory cell while improving the endurance, given the utilization of standard fabrication processes.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a non-volatile semiconductor memory cell having a separate tunnel window, the method includes the steps of:
forming a tunnel window cell by forming a tunnel zone, a tunnel layer, a tunnel window memory layer, a dielectric tunnel window layer and a tunnel window control electrode layer;
forming a transistor memory cell with a channel zone, a gate layer, a memory layer, a dielectric layer and a control electrode layer;
forming the tunnel window cell and the transistor memory cell in active regions of a semiconductor substrate such that the transistor memory cell and the tunnel window cell are separated from one another;
forming a connecting region for connecting the tunnel window cell with the transistor memory cell in an inactive region of the semiconductor substrate; and
doping the tunnel zone in an active region of the tunnel window cell subsequent to forming the tunnel layer.
In particular by forming tunnel zones in the active region of the tunnel window cells subsequent to the formation of the tunnel layer, it is possible to create a non-volatile semiconductor memory cell which is equal to a conventional EEPROM cell with respect to its endurance, i.e. program/clear cycles, but significantly improved with respect to its space requirements. Beyond this, a memory cell so fabricated can easily be realized in a common integrated circuit with conventional FLASH-EPROM cells using standard processes. The useful voltages (program/clear/read voltages) can be the same for a wide variety of forms of non-volatile semiconductor memory cells.
The tunnel zones are formed by implantation in self-aligning fashion with the aid of at least one layer of the tunnel window cell. In particular, for high-density circuits with structural sizes xe2x89xa61 xcexcm, memory cells can be easily and reliably fabricated in this way. The implantation can be performed vertically and/or diagonally into the region beneath the tunnel layer, whereby implantation zones completely below the tunnel layer touch or are formed so close to one another that their space charge zones or depletion zones perform what is known as a punch-through effect when an operating voltage is applied. In other words, the tunnel zones are configured such that space charge zones of the implantation zones extend completely into a region under the tunnel layer when an operating voltage is applied. This way, a very homogenous tunnel zone is obtained beneath the tunnel layer, which is comparable to a tunnel zone that is implanted beforehand, so that uniform field intensities arise during programming/erasing, and the endurance is improved.
Expediently, a floating gate connecting region and a control electrode connecting region are formed simultaneously with the appertaining floating gate layers and control electrode layers of the tunnel window cell and the transistor memory cell, thereby guaranteeing a further simplification of the fabrication process.
Another mode of the method according to the invention includes the step of forming a memory layer connecting region simultaneously with the memory layer and the tunnel window memory layer.
Yet another mode of the method according to the invention includes the step of forming a control electrode connecting region simultaneously with the control electrode layer and the tunnel window control electrode layer.
Another mode of the method according to the invention includes the step of forming the tunnel zone by using an MD (Matrix Drain) implantation or an LDD (Lightly Doped Drain) implantation.
A further mode of the method according to the invention includes the step of forming an EEPROM memory cell from the transistor memory cell and the tunnel window cell.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating a non-volatile semiconductor memory cell with a separate tunnel window, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.